With evolution of mobile communication systems, Quality of Service (QoS) for users has become the primary issue of operators. The QoS affects service performance and determines users' satisfaction with services. One important aspect for improving the QoS is the time delay when setting up connections and allocating channels, and the existence of frequent services of small data packets, therefore, it is necessary to consider making the common channels work more effectively, for example, by reducing the signaling delay in the uplink and downlink. By introducing the downlink High Speed Packet Access (HSPA), 3rd Generation Partnership Project (3GPP) standard has shortened the downlink signaling delay in the CELL_FACH, Cell_Paging_Channel (CELL_PCH), or UTRAN Registration Area_Paging Channel (URA_PCH) state, however, the issue of the uplink signaling delay still exists.
To shorten the uplink signaling delay, the following aspects need to be considered:
(1) reducing the waiting time of the user plane and control plane in the idle mode, CELL_FACH, CELL_PCH, or URA_PCH state;
(2) improving the peak rate in the CELL_FACH state;
(3) shortening the delay in transition between the idle, CELL_FACH, CELL_PCH, URA_PCH, and Cell_Dedicated Channel (CELL_DCH) states.
To achieve the above objective, the 3GPP standard has introduced the Enhanced Dedicated Channel (E-DCH) in the CELL_FACH state and idle mode, that is, the High Speed Uplink Packet Access (HSUPA) can be used in the idle mode or CELL_FACH state. Application of the HUSPA in the idle mode and CELL_FACH state is called the uplink enhanced CELL_FACH technology.
The uplink enhanced CELL_FACH technology follows the principle as follows: random access still adopts the access process of the Physical Random Access Channel (PRACH) but the channel type changes; that is, the E-DCH is used in the idle mode or CELL_FACH state, logical channels such as Common Control Channel (CCCH), Dedicated Control Channel (DCCH), or Dedicated Traffic Channel (DTCH) can be mapped to the E-DCH and then transmitted. The E-DCH is mapped to the E-DCH Dedicated Physical Data Channel (E-DPDCH). The E-DPDCH works basing on the E-DCH Dedicated Physical Control Channel (E-DPCCH). The E-DPCCH is based on the Dedicated Physical Control Channel (DPCCH). Therefore, in the enhanced CELL_FACH state, a DPCCH is required in the uplink, and for collaborating with the uplink DPCCH to perform link synchronization, a Fractional Dedicated Physical Control Channel (F-DPCH) is also required in the downlink.
According to the current 3GPP, Uu interface defines that No.0 slot format is used by the F-DPCH used by the UE in the idle mode and CELL_FACH state, so it is needless for the radio network controller (RNC) to notify the Node B of the slot format through signaling. However, on the Iub interface, there is a configuration cell for configuring the F-DPCH slot format used in the idle mode or CELL_FACH state, and there are 10 types of slot formats that can be configured for the F-DPCH, and the Iub interface protocol does not define that the Node B can only use No.0 slot format.
FIG. 1 is a schematic diagram of E-DPCH frame formats defined in the 3GPP protocol. Referring to FIG. 1, among the defined frame formats, Noff1 bits and Noff2 bits are non-transmission bits. The slot formats defined in the 3GPP protocols for the F-DPCH are as shown in Table 1.
TABLE 1SlotChannelChannelNOFF1NTPCNOFF2FormatBit RateSymbol RateBits/Bits/Bits/Bits/#i(kbps)(ksps)FSlotSlotSlotSlot031.5256202216131.5256204214231.5256206212331.5256208210431.5256201028531.5256201226631.5256201424731.5256201622831.5256201820931.5256200218
It can be see from the frame formats and the slot formats shown in Table 1, No.0 slot format differs from other formats in that the locations the Transmit Power Control (TPC) bits in a slot are different. Consequently, if the RNC configures a non-No.0 slot format for the F-DPCH, the Node B uses the non-No.0 slot format configured by the RNC to transmit the F-DPCH, but the UE fixedly uses No.0 slot format to receive the F-DPCH. As a result, the UE cannot correctly receive the TPC bits information and thus it cannot perform inner loop power control properly, thereby causing link failure.